1. Field of the Invention
The present invention relates to data processing systems and, more particularly, to devices used to interface internal components of a microprocessor-based system.
2. Description of Related Art
Conventional computer systems generally include one or more central processing units (CPU's) providing primary controls of the computer system. These CPUs are connected through a host bus to a Host/PCI bus bridge that interfaces among the CPU, the main memory and the peripheral components. The Host/PCI bridge is connected to a peripheral component interface (PCI) bus, which is connected to peripheral components such as local area networks, graphics cards and mass media devices.
Also included in conventional systems is a PCI/ISA bridge that interfaces the PCI bus with an industry standard architecture (ISA) bus. The ISA bus interfaces with peripheral devices such as hard drives, CD ROMs, keyboard input, mouse input, etc. Mass storage components are serviced by the ISA bus and are accessible by the CPU through the PCI/ISA bridge. These peripheral components are much slower than components connected to the PCI bus. Components on the PCI bus usually operate at an optimum 33 MHz, where components on the ISA bus typically run at 8 MHz. Therefore, the bridge acts as a PCI/ISA bridge so that the slower peripheral components serviced by the ISA bus are made compatible with the main system.
In a typical data transfer sequence from the mass storage devices, a CPU sends an Integrated Device Electronics (IDE) data transfer command through the host bus which in turn sends the command through the host/PCI bus bridge to the PCI bus. From there, the PCI bus sends a command through the PCI/ISA bridge. The PCI/ISA bridge then takes over the IDE data transfer operations. The command from the CPU programs the PCI/ISA bridge to carry out the IDE data transfer operation through predetermined procedures. The PCI/ISA bridge is connected to an IDE circuitry that interfaces the mass storage devices such as hard drives, CD ROMs, tape backups, etc. The IDE circuitry is connected to the traditional computer hard drive through a ribbon cable. In conventional systems, more than one set of IDE circuitry can exist so that the system has access to multiple mass storage devices. In an IDE data transfer cycle, the PCI/ISA bridge accesses the IDE circuitry through a series of data lines that access the mass storage devices through the IDE circuitry. Typically, separate pins of the PCI/ISA bridge are used to transfer this data.
Aside from access to peripheral devices, the ISA bus also includes an ISA expansion memory that requires refresh. During refresh, the entire ISA bus is taken out of operation so that the refresh cycles can commence. During these cycles, typically once every 15 .mu.s, or 1/15 of the total operating time, no functions can be executed on the ISA bus.
Optimization of a computer system as a whole requires that communication lines and connectors be kept to a minimum in order to maintain speed, efficiency, simplicity and manufacturability. One way of optimizing a computer system is to multiplex lines to share paths and connections. Both the IDE circuitry and the ISA bus require multitudes of paths and connections including data, address and control lines. A great deal of circuitry and space could be saved if nonconflicting portions of these two systems could be multiplexed. Unfortunately, conventional methods cannot accomplish this without stopping IDE data transfers during ISA refresh cycles.
Accordingly, it would be of great use to the computer industry to successfully multiplex portions of the IDE circuitry with nonconflicting portions of the ISA bus. As will be seen, the present invention accomplishes this in a simple and elegant manner.